Introduction to Lethal Circuit Transformations

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00235708" target="_blank" >RIV/68407700:21240/15:00235708 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1063/1.4938891" target="_blank" >http://dx.doi.org/10.1063/1.4938891</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1063/1.4938891" target="_blank" >10.1063/1.4938891</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Introduction to Lethal Circuit Transformations

Popis výsledku v původním jazyce

Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network ina reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic syn

Název v anglickém jazyce

Introduction to Lethal Circuit Transformations

Popis výsledku anglicky

Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network ina reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic syn

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

AIP Conference Proceedings

ISBN

978-0-7354-1349-8

ISSN

0094-243X

e-ISSN

—

Počet stran výsledku

4

Strana od-do

1-4

Název nakladatele

AIP Publishing

Místo vydání

Melville, NY

Místo konání akce

Athens

Datum konání akce

20. 3. 2015

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000371804300120