SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F19%3A00337144" target="_blank" >RIV/68407700:21240/19:00337144 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/00216305:26230/19:PU136084

Výsledek na webu

<a href="https://doi.org/10.1142/S0218126619400103" target="_blank" >https://doi.org/10.1142/S0218126619400103</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1142/S0218126619400103" target="_blank" >10.1142/S0218126619400103</a>

Jazyk výsledku

angličtina

Název v původním jazyce

SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support

Popis výsledku v původním jazyce

This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one or enumerate all optimum implementations, while the allowed target gate types and gates costs can be arbitrarily specified. Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable of performing two or more different intended functions, depending on instantaneous conditions in the target operating environment. In this paper we propose the first method ever, generating provably size-optimal polymorphic circuits. Scalability and feasibility of the method are documented by providing experimental results for all NPN-equivalence classes of four-input functions implemented in AND–Inverter and AND–XOR–Inverter logics without polymorphic behavior support being used and for all pairs of NPN–equivalence classes of three-input functions for polymorphic circuits. Finally, several smaller benchmark circuits were synthesized optimally, both in standard and polymorphic logics.

Název v anglickém jazyce

SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support

Popis výsledku anglicky

This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one or enumerate all optimum implementations, while the allowed target gate types and gates costs can be arbitrarily specified. Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable of performing two or more different intended functions, depending on instantaneous conditions in the target operating environment. In this paper we propose the first method ever, generating provably size-optimal polymorphic circuits. Scalability and feasibility of the method are documented by providing experimental results for all NPN-equivalence classes of four-input functions implemented in AND–Inverter and AND–XOR–Inverter logics without polymorphic behavior support being used and for all pairs of NPN–equivalence classes of three-input functions for polymorphic circuits. Finally, several smaller benchmark circuits were synthesized optimally, both in standard and polymorphic logics.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

ISSN

0218-1266

e-ISSN

1793-6454

Svazek periodika

28

Číslo periodika v rámci svazku

Supp01

Stát vydavatele periodika

SG - Singapurská republika

Počet stran výsledku

29

Strana od-do

—

Kód UT WoS článku

000503001600011

EID výsledku v databázi Scopus

2-s2.0-85067369067