A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00319199" target="_blank" >RIV/68407700:21240/18:00319199 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.cambridgescholars.com/further-improvements-in-the-boolean-domain" target="_blank" >https://www.cambridgescholars.com/further-improvements-in-the-boolean-domain</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization

Popis výsledku v původním jazyce

We present experimental evidence that logic synthesis procedure, especially those based on resynthesis, do net perform well when the original (designer-given) structure of input description is lost. As such performance has not been observed otherwise, we must conclude that such operation is outside of the intended range, and that synthesis examples with their original structure lost are not valid for evaluation of synthesis procedures. We also outline other causes that may render an example invalid. We, however, document that such losses did occur with circuit examples circulating in the logic synthesis community. Therefore, we have to suggest what constitutes prudence in examples collection.

Název v anglickém jazyce

A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization

Popis výsledku anglicky

We present experimental evidence that logic synthesis procedure, especially those based on resynthesis, do net perform well when the original (designer-given) structure of input description is lost. As such performance has not been observed otherwise, we must conclude that such operation is outside of the intended range, and that synthesis examples with their original structure lost are not valid for evaluation of synthesis procedures. We also outline other causes that may render an example invalid. We, however, document that such losses did occur with circuit examples circulating in the logic synthesis community. Therefore, we have to suggest what constitutes prudence in examples collection.

Druh

C - Kapitola v odborné knize

CEP obor

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OECD FORD obor

20206 - Computer hardware and architecture

Projekt

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Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název knihy nebo sborníku

Further Improvements in the Boolean Domain

ISBN

978-1-5275-0371-7

Počet stran výsledku

22

Strana od-do

280-301

Počet stran knihy

536

Název nakladatele

Cambridge Scholars Publishing

Místo vydání

Newcastle upon Tyne

Kód UT WoS kapitoly

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