A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00375937" target="_blank" >RIV/68407700:21240/24:00375937 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/DDECS60919.2024.10508902" target="_blank" >https://doi.org/10.1109/DDECS60919.2024.10508902</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS60919.2024.10508902" target="_blank" >10.1109/DDECS60919.2024.10508902</a>

Jazyk výsledku

angličtina

Název v původním jazyce

A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks

Popis výsledku v původním jazyce

Small quantized neural networks with strong requirements on throughput and latency can be translated into combinational logic circuits and synthesized by logic design tools. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. The first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. The response to activation values that have not occurred in the training set remain unspecified. The other approach uses a complete set of activation values at the input of the examined part. Our study aims to quantify the inaccuracy of the first method, the influence of logic minimization used on accuracy, and the impact on the final synthesized circuit. We also document the quantitative changes in quantized networks.

Název v anglickém jazyce

A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks

Popis výsledku anglicky

Small quantized neural networks with strong requirements on throughput and latency can be translated into combinational logic circuits and synthesized by logic design tools. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. The first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. The response to activation values that have not occurred in the training set remain unspecified. The other approach uses a complete set of activation values at the input of the examined part. Our study aims to quantify the inaccuracy of the first method, the influence of logic minimization used on accuracy, and the impact on the final synthesized circuit. We also document the quantitative changes in quantized networks.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

ISBN

979-8-3503-5934-3

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

86-91

Název nakladatele

IEEE

Místo vydání

Piscataway

Místo konání akce

Kielce

Datum konání akce

3. 4. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001227439800003