Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00378095" target="_blank" >RIV/68407700:21240/24:00378095 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/DSD64264.2024.00011" target="_blank" >https://doi.org/10.1109/DSD64264.2024.00011</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD64264.2024.00011" target="_blank" >10.1109/DSD64264.2024.00011</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation

Popis výsledku v původním jazyce

The development of electrostatically doped graphene PN-junctions shows promise for creating efficient low-power, high-speed circuits. In recent years, there has been a considerable interest in the synthesis of graphene PN junction logic circuits. However, existing synthesis methods lack assessment based on technology-specific cost metrics (e.g., the number of graphene PN junction gates, constant inputs), leading to insufficiently addressed design objectives. In this paper, we introduce synthesis approaches for graphene PN-junction circuits based on Sum-of-Products (SoP) and Exclusive Sum-of-Products (ESoP) function representations. Experimental results indicate that ESoP-based synthesis significantly reduces the number of graphene PN junction gates, constant inputs, and switching activity compared to SoP-based approaches. Overall, ESoP-based synthesis is deemed more suitable than SoP-based methods for designing graphene PN-junction logic circuits.

Název v anglickém jazyce

Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation

Popis výsledku anglicky

The development of electrostatically doped graphene PN-junctions shows promise for creating efficient low-power, high-speed circuits. In recent years, there has been a considerable interest in the synthesis of graphene PN junction logic circuits. However, existing synthesis methods lack assessment based on technology-specific cost metrics (e.g., the number of graphene PN junction gates, constant inputs), leading to insufficiently addressed design objectives. In this paper, we introduce synthesis approaches for graphene PN-junction circuits based on Sum-of-Products (SoP) and Exclusive Sum-of-Products (ESoP) function representations. Experimental results indicate that ESoP-based synthesis significantly reduces the number of graphene PN junction gates, constant inputs, and switching activity compared to SoP-based approaches. Overall, ESoP-based synthesis is deemed more suitable than SoP-based methods for designing graphene PN-junction logic circuits.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2024 27th Euromicro Conference on Digital System Design

ISBN

979-8-3503-8038-5

ISSN

2639-3859

e-ISSN

2771-2508

Počet stran výsledku

8

Strana od-do

11-18

Název nakladatele

IEEE Computer Society

Místo vydání

Los Alamitos

Místo konání akce

Paris

Datum konání akce

28. 8. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001414927800002