Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F23%3A00366489" target="_blank" >RIV/68407700:21240/23:00366489 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/ISDCS58735.2023.10153524" target="_blank" >https://doi.org/10.1109/ISDCS58735.2023.10153524</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISDCS58735.2023.10153524" target="_blank" >10.1109/ISDCS58735.2023.10153524</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring

Popis výsledku v původním jazyce

Graphene PN Junction (GPNJ) logic circuits received significant attention from the researchers thanks to the availability of electrostatically doped graphene PN Junction (GPNJ) device- a promising one for designing low-power, high-speed circuits. Several design approaches for GPNJ logic circuits realizing important arithmetic and arbitrary Boolean functions exist in literature. However, no detailed evaluations of the resulting circuit complexities with respect to relevant cost metrics are reported. It remains open, how do we synthesize GPNJ logic circuits with minimal switching activity, an essential cost metric influencing the dynamic power dissipation in the resulting circuits. In this paper, we introduce a synthesis approach for GPNJ logic circuits that interconnects a set of GPNJ devices in parallel. Such parallel circuit structures ensure the reduction of switching activity in the resulting GPNJ logic circuits. To the best of our knowledge, so far only one research work discussed the computation of switching activity of GPNJ logic circuits. Experimental evaluations confirm that an average 67.35% reduction in switching activity can be achieved using the proposed approach over the existing one.

Název v anglickém jazyce

Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring

Popis výsledku anglicky

Graphene PN Junction (GPNJ) logic circuits received significant attention from the researchers thanks to the availability of electrostatically doped graphene PN Junction (GPNJ) device- a promising one for designing low-power, high-speed circuits. Several design approaches for GPNJ logic circuits realizing important arithmetic and arbitrary Boolean functions exist in literature. However, no detailed evaluations of the resulting circuit complexities with respect to relevant cost metrics are reported. It remains open, how do we synthesize GPNJ logic circuits with minimal switching activity, an essential cost metric influencing the dynamic power dissipation in the resulting circuits. In this paper, we introduce a synthesis approach for GPNJ logic circuits that interconnects a set of GPNJ devices in parallel. Such parallel circuit structures ensure the reduction of switching activity in the resulting GPNJ logic circuits. To the best of our knowledge, so far only one research work discussed the computation of switching activity of GPNJ logic circuits. Experimental evaluations confirm that an average 67.35% reduction in switching activity can be achieved using the proposed approach over the existing one.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Výzkumné centrum informatiky</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 6th International Symposium on Devices, Circuits and Systems

ISBN

979-8-3503-1504-2

ISSN

2767-9837

e-ISSN

2767-9837

Počet stran výsledku

6

Strana od-do

—

Název nakladatele

Hiroshima University

Místo vydání

Hiroshima

Místo konání akce

Virtual conference

Datum konání akce

29. 5. 2023

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

—