Programmable delay controller allowing frequency synthesis and arbitrary binary waveform generation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F13%3A00214180" target="_blank" >RIV/68407700:21340/13:00214180 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/EFTF-IFC.2013.6702147" target="_blank" >http://dx.doi.org/10.1109/EFTF-IFC.2013.6702147</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/EFTF-IFC.2013.6702147" target="_blank" >10.1109/EFTF-IFC.2013.6702147</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Programmable delay controller allowing frequency synthesis and arbitrary binary waveform generation

Popis výsledku v původním jazyce

Design of a programmable delay controller (PDC) within an aerospace-compatible field-programmable gate array (FPGA) fabric is presented. Although PDC is a common digital block nowadays, the possibility to use it for low-jitter arbitrary frequency generation constrained only by minimum edge-to-edge time still seems to be uncovered. The novel idea of the developed PDC is seamless line delay switching at sampling frequencies corresponding to the generated output frequency, unleashing a possibility of arbitrary binary waveform (frequency) generation. The maximum frequency is constrained only by the FPGA fabric performance, and by idle delay of available multiplexers. Glitch-free operation with no unintentional edges is employed for proper PDC control signal switching. The overall output signal jitter is composed solely of the jitter of input signal and propagation jitter of the delay elements (?max = 4.1 ps RMS). Measured resolution of the PDC is ???max/2 = ?7.5 ps. Measured temperature dr

Název v anglickém jazyce

Programmable delay controller allowing frequency synthesis and arbitrary binary waveform generation

Popis výsledku anglicky

Design of a programmable delay controller (PDC) within an aerospace-compatible field-programmable gate array (FPGA) fabric is presented. Although PDC is a common digital block nowadays, the possibility to use it for low-jitter arbitrary frequency generation constrained only by minimum edge-to-edge time still seems to be uncovered. The novel idea of the developed PDC is seamless line delay switching at sampling frequencies corresponding to the generated output frequency, unleashing a possibility of arbitrary binary waveform (frequency) generation. The maximum frequency is constrained only by the FPGA fabric performance, and by idle delay of available multiplexers. Glitch-free operation with no unintentional edges is employed for proper PDC control signal switching. The overall output signal jitter is composed solely of the jitter of input signal and propagation jitter of the delay elements (?max = 4.1 ps RMS). Measured resolution of the PDC is ???max/2 = ?7.5 ps. Measured temperature dr

Druh

D - Stať ve sborníku

CEP obor

JB - Senzory, čidla, měření a regulace

OECD FORD obor

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Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach<br>I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2013 Joint European Frequency and Time Forum and International Frequency Control Symposium (EFTF/IFC)

ISBN

978-1-4799-0342-9

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

192-195

Název nakladatele

IEEE Ultrasonics, Ferroelectrics, and Frequency Control Society

Místo vydání

Piscataway

Místo konání akce

Prague

Datum konání akce

21. 7. 2013

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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