Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F18%3A00374254" target="_blank" >RIV/68407700:21340/18:00374254 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/NSSMIC.2018.8824486" target="_blank" >https://doi.org/10.1109/NSSMIC.2018.8824486</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/NSSMIC.2018.8824486" target="_blank" >10.1109/NSSMIC.2018.8824486</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC

Popis výsledku v původním jazyce

The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50x50 or 25x100 mu m(2)) and large pixel chip size (similar to 2x2 cm(2)), high hit rate (3 GHz/cm(2)), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (similar to 12.5 mu s), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400x192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed.

Název v anglickém jazyce

Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC

Popis výsledku anglicky

The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50x50 or 25x100 mu m(2)) and large pixel chip size (similar to 2x2 cm(2)), high hit rate (3 GHz/cm(2)), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (similar to 12.5 mu s), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400x192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

—

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC)

ISBN

978-1-5386-8494-8

ISSN

2577-0829

e-ISSN

2577-0829

Počet stran výsledku

4

Strana od-do

1-4

Název nakladatele

Institute of Electrical and Electronics Engineers, Inc.

Místo vydání

—

Místo konání akce

Sydney

Datum konání akce

10. 11. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000601256000220