Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216275%3A25530%2F22%3A39919612" target="_blank" >RIV/00216275:25530/22:39919612 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9764899" target="_blank" >https://ieeexplore.ieee.org/document/9764899</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/RADIOELEKTRONIKA54537.2022.9764899" target="_blank" >10.1109/RADIOELEKTRONIKA54537.2022.9764899</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications

Popis výsledku v původním jazyce

Nowadays demand for artificial intelligence (AI) enabled mobile platforms is increasing. From healthcare services to defense and from remote to urban area, there is a huge demand of secured and power efficient devices. The performance of these platforms can be enhanced by providing an efficient compute engine. These compute engines perform a huge amount of matrix operations. The most popular choice for large matrix computation is a systolic array. In general, the systolic array performance degrades for the large input matrices, due to the trade off between resource utilization and computation delay. To address this issue, we need a systolic array with a control unit to re-configure the array according to the requirement of the computation. Computation array can be further improved by handling the negative weights and reduce the MAC operations. In this paper, we proposed a generalized bfloat16 based systolic array in which the sign of the partial sum (PS) is predicted before computation. The PS sign aids in network pruning which enhances system performance. The proposed system is implemented on a Virtex-7 FPGA board and it performs 2.21 similar to and 4.19x better in terms of area and power compared to single-precision based systolic array.

Název v anglickém jazyce

Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications

Popis výsledku anglicky

Nowadays demand for artificial intelligence (AI) enabled mobile platforms is increasing. From healthcare services to defense and from remote to urban area, there is a huge demand of secured and power efficient devices. The performance of these platforms can be enhanced by providing an efficient compute engine. These compute engines perform a huge amount of matrix operations. The most popular choice for large matrix computation is a systolic array. In general, the systolic array performance degrades for the large input matrices, due to the trade off between resource utilization and computation delay. To address this issue, we need a systolic array with a control unit to re-configure the array according to the requirement of the computation. Computation array can be further improved by handling the negative weights and reduce the MAC operations. In this paper, we proposed a generalized bfloat16 based systolic array in which the sign of the partial sum (PS) is predicted before computation. The PS sign aids in network pruning which enhances system performance. The proposed system is implemented on a Virtex-7 FPGA board and it performs 2.21 similar to and 4.19x better in terms of area and power compared to single-precision based systolic array.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LTAIN19100" target="_blank" >LTAIN19100: Vývoj bezkontaktní technologie pro inteligentní ochranu zájmových prostor</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2022 32ND INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA)

ISBN

978-1-72818-686-3

ISSN

—

e-ISSN

—

Počet stran výsledku

5

Strana od-do

44-48

Název nakladatele

IEEE

Místo vydání

NEW YORK

Místo konání akce

Kosice

Datum konání akce

21. 4. 2022

Typ akce podle státní příslušnosti

CST - Celostátní akce

Kód UT WoS článku

000856002200011