Fault Tolerant BLDC Motor Control for Hall Sensors Failure

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26210%2F15%3APU115738" target="_blank" >RIV/00216305:26210/15:PU115738 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Fault Tolerant BLDC Motor Control for Hall Sensors Failure

Popis výsledku v původním jazyce

In most brushless direct current (BLDC) motor drives, there are three hall sensors as a position reference. This paper presents a method that allows the operation of a BLDC motor with one faulty hall sensor. The situations considered are when the output from a hall sensor stays continuously at low or high levels, or a short-time pulse appears on a hall sensor signal. For fault detection, identification of a faulty signal and generating a substitute signal, this method only needs the information from the hall sensors. So this method can be added as a standalone subsystem to existing drives. The paper provides many simulations on how the presented method reacts for various types of faults. An experimental evaluation is provided too. Due to the demand to operate at a high speed, the method is implemented into the FPGA.

Název v anglickém jazyce

Fault Tolerant BLDC Motor Control for Hall Sensors Failure

Popis výsledku anglicky

In most brushless direct current (BLDC) motor drives, there are three hall sensors as a position reference. This paper presents a method that allows the operation of a BLDC motor with one faulty hall sensor. The situations considered are when the output from a hall sensor stays continuously at low or high levels, or a short-time pulse appears on a hall sensor signal. For fault detection, identification of a faulty signal and generating a substitute signal, this method only needs the information from the hall sensors. So this method can be added as a standalone subsystem to existing drives. The paper provides many simulations on how the presented method reacts for various types of faults. An experimental evaluation is provided too. Due to the demand to operate at a high speed, the method is implemented into the FPGA.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

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Návaznosti

R - Projekt Ramcoveho programu EK

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Automation, Computing and Manufacturing for New Economic Growth

ISBN

978-0-9926801-0-7

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

317-322

Název nakladatele

Neuveden

Místo vydání

Neuveden

Místo konání akce

Glasgow

Datum konání akce

11. 9. 2015

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000380609400054