A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F06%3APU57577" target="_blank" >RIV/00216305:26220/06:PU57577 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC

Popis výsledku v původním jazyce

The article describes a new background calibration technique, which is used in a new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the same purpose. The basic problems coupled to SC, such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities, have been taken into account during a design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account, too.

Název v anglickém jazyce

A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC

Popis výsledku anglicky

The article describes a new background calibration technique, which is used in a new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the same purpose. The basic problems coupled to SC, such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities, have been taken into account during a design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account, too.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2006

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

ISCCSP Proceedings 2006

ISBN

2-908849-17-8

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

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Název nakladatele

IEEE CAS

Místo vydání

Marrakech, Maroko

Místo konání akce

Marrakech

Datum konání akce

13. 3. 2006

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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