Efficient Method for Overflow Detection and Correction in Residue Number System

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU99361" target="_blank" >RIV/00216305:26220/12:PU99361 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Efficient Method for Overflow Detection and Correction in Residue Number System

Popis výsledku v původním jazyce

This paper presents a new efficient method for overflow detection and correction in the addition of two numbers in the residue number system (RNS). Overflow is one of the most challenging topics in this system that can overcome and greatly limit its main features, such as no carry propagation, parallel arithmetic and high speed calculations. The proposed design can be used with any system that has 2n as one of its moduli (i.e. has an even dynamic range), such as: (2n–1, 2n, 2n+1), (2n–1, 2n, 22n+1), etc. The proposed method depends on a very simple structure that provides fast and accurate detection and corrections of the overflow. The presented technique was synthesized and implemented on Spartran-3 FPGA. The simulation and implementation results have proved the efficiency of this method. A detailed comparison in terms of time and area consumption, using the standard unit-gate model, is presented.

Název v anglickém jazyce

Efficient Method for Overflow Detection and Correction in Residue Number System

Popis výsledku anglicky

This paper presents a new efficient method for overflow detection and correction in the addition of two numbers in the residue number system (RNS). Overflow is one of the most challenging topics in this system that can overcome and greatly limit its main features, such as no carry propagation, parallel arithmetic and high speed calculations. The proposed design can be used with any system that has 2n as one of its moduli (i.e. has an even dynamic range), such as: (2n–1, 2n, 2n+1), (2n–1, 2n, 22n+1), etc. The proposed method depends on a very simple structure that provides fast and accurate detection and corrections of the overflow. The presented technique was synthesized and implemented on Spartran-3 FPGA. The simulation and implementation results have proved the efficiency of this method. A detailed comparison in terms of time and area consumption, using the standard unit-gate model, is presented.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

<a href="/cs/project/FR-TI3%2F485" target="_blank" >FR-TI3/485: Sledování stavu stavebních konstrukcí pomocí elektricky vodivých prvků s modifikovanou cementovou matricí</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2012

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Electronic Devices and Systems IMAPS CS International Conference 2012

ISBN

978-80-214-4539-0

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

183-188

Název nakladatele

Neuveden

Místo vydání

Brno

Místo konání akce

Brno

Datum konání akce

28. 6. 2012

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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