Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU121520" target="_blank" >RIV/00216305:26220/18:PU121520 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.24200/sci.2017.4377" target="_blank" >http://dx.doi.org/10.24200/sci.2017.4377</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.24200/sci.2017.4377" target="_blank" >10.24200/sci.2017.4377</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

Popis výsledku v původním jazyce

In this work, a new realization topology of the low-voltage ultra-low-power quadrature oscillator is presented. This quadrature oscillator utilizes only two active elements, namely differential voltage current conveyor (DVCC), and five passive ones, all of them are grounded, which is recommended for the integrated circuit implementation. The DVCC is based on quasi-floating-gate MOS transistor, which is a distinct technique from the conventional one, featuring with operation at low-voltage and ultra-low-power conditions; hence the proposed DVCC works with low supply voltage of ± 400 mV and consumes power of merely 6.6 µW. Thanks to these features the total power dissipation of the oscillator is only 0.28 mW. The simulation results using 0.18 µm TSMC CMOS technology are included in order to prove the design correctness.

Název v anglickém jazyce

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

Popis výsledku anglicky

In this work, a new realization topology of the low-voltage ultra-low-power quadrature oscillator is presented. This quadrature oscillator utilizes only two active elements, namely differential voltage current conveyor (DVCC), and five passive ones, all of them are grounded, which is recommended for the integrated circuit implementation. The DVCC is based on quasi-floating-gate MOS transistor, which is a distinct technique from the conventional one, featuring with operation at low-voltage and ultra-low-power conditions; hence the proposed DVCC works with low supply voltage of ± 400 mV and consumes power of merely 6.6 µW. Thanks to these features the total power dissipation of the oscillator is only 0.28 mW. The simulation results using 0.18 µm TSMC CMOS technology are included in order to prove the design correctness.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/LO1401" target="_blank" >LO1401: Interdisciplinární výzkum bezdrátových technologií</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

SCIENTIA IRANICA

ISSN

1026-3098

e-ISSN

2345-3605

Svazek periodika

25

Číslo periodika v rámci svazku

6, IF: 0.475

Stát vydavatele periodika

IR - Íránská islámská republika

Počet stran výsledku

13

Strana od-do

„3477“-„3489 “

Kód UT WoS článku

000454261500005

EID výsledku v databázi Scopus

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