Quadrature oscillator based on a novel low-voltage ultra-low-power quasi-floating-gate DVCC

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F18%3A00329563" target="_blank" >RIV/68407700:21460/18:00329563 - isvavai.cz</a>

Výsledek na webu

<a href="http://scientiairanica.sharif.edu/article_4377.html" target="_blank" >http://scientiairanica.sharif.edu/article_4377.html</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.24200/sci.2017.4377" target="_blank" >10.24200/sci.2017.4377</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Quadrature oscillator based on a novel low-voltage ultra-low-power quasi-floating-gate DVCC

Popis výsledku v původním jazyce

In this work, a new realization topology of the low-voltage ultra-low-power quadrature oscillator is presented. This quadrature oscillator utilizes only two active elements, namely, Differential Voltage Current Conveyors (DVCCs), and five passive ones. All of the elements are grounded, which is recommended for integrated circuit implementation. The DVCC is based on quasi-floating-gate MOS transistor, which is a distinct technique from the conventional one, featuring operation at low-voltage and ultra-low-power conditions; hence, the proposed DVCC works with low supply voltage of +/- 400 mV and consumes power of merely 6.6 a mu W. Thanks to these features, the total power dissipation of the oscillator is only 0.28 mW. The simulation results using 0.18-mu m TSMC CMOS technology are included in order to prove validity of the design. (C) 2018 Sharif University of Technology. All rights reserved.

Název v anglickém jazyce

Quadrature oscillator based on a novel low-voltage ultra-low-power quasi-floating-gate DVCC

Popis výsledku anglicky

In this work, a new realization topology of the low-voltage ultra-low-power quadrature oscillator is presented. This quadrature oscillator utilizes only two active elements, namely, Differential Voltage Current Conveyors (DVCCs), and five passive ones. All of the elements are grounded, which is recommended for integrated circuit implementation. The DVCC is based on quasi-floating-gate MOS transistor, which is a distinct technique from the conventional one, featuring operation at low-voltage and ultra-low-power conditions; hence, the proposed DVCC works with low supply voltage of +/- 400 mV and consumes power of merely 6.6 a mu W. Thanks to these features, the total power dissipation of the oscillator is only 0.28 mW. The simulation results using 0.18-mu m TSMC CMOS technology are included in order to prove validity of the design. (C) 2018 Sharif University of Technology. All rights reserved.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

SCIENTIA IRANICA

ISSN

1026-3098

e-ISSN

—

Svazek periodika

25

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

13

Strana od-do

3477-3489

Kód UT WoS článku

000454261500005

EID výsledku v databázi Scopus

2-s2.0-85059180089