Versatile Chirp Sine Generator on Fix-point FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F20%3APU134546" target="_blank" >RIV/00216305:26220/20:PU134546 - isvavai.cz</a>

Výsledek na webu

<a href="https://ojs.cvut.cz/ojs/index.php/ap/article/view/6049" target="_blank" >https://ojs.cvut.cz/ojs/index.php/ap/article/view/6049</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.14311/AP.2020.60.0462" target="_blank" >10.14311/AP.2020.60.0462</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Versatile Chirp Sine Generator on Fix-point FPGA

Popis výsledku v původním jazyce

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

Název v anglickém jazyce

Versatile Chirp Sine Generator on Fix-point FPGA

Popis výsledku anglicky

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

Druh

J_SC - Článek v periodiku v databázi SCOPUS

CEP obor

—

OECD FORD obor

20205 - Automation and control systems

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Acta Polytechnica (on-line)

ISSN

1210-2709

e-ISSN

1805-2363

Svazek periodika

60

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

CZ - Česká republika

Počet stran výsledku

7

Strana od-do

462-468

Kód UT WoS článku

—

EID výsledku v databázi Scopus

2-s2.0-85099667611