On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU145341" target="_blank" >RIV/00216305:26220/22:PU145341 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21240/22:00359271

Výsledek na webu

<a href="https://dl.acm.org/doi/abs/10.1145/3538969.3544423" target="_blank" >https://dl.acm.org/doi/abs/10.1145/3538969.3544423</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/3538969.3544423" target="_blank" >10.1145/3538969.3544423</a>

Jazyk výsledku

angličtina

Název v původním jazyce

On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography

Popis výsledku v původním jazyce

Currently, many post-quantum cryptography schemes have been implemented on various hardware platforms in order to provide efficient solutions in cybersecurity services. As researchers and hardware developers focus primarily on designs providing small latency and requiring fewer hardware resources, their implementations could seldom omit protection techniques against various physical attacks. This paper studies potential attacks on the cryptography implementations that run on Field-Programmable Gate Array (FPGA) platforms. We mainly analyze how Post-Quantum Cryptography (PQC) implementations could be vulnerable on various platforms. Further, we aim at the FPGA-based implementations of National Institute of Standards and Technology (NIST)’s PQC competition finalists. Our study should present to developers the current overview of attacks and countermeasures that can be implemented on specific PQC schemes on FPGA platforms. Moreover, we present novel implementation of one universal countermeasure component and reveal additional resources that are needed.

Název v anglickém jazyce

On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography

Popis výsledku anglicky

Currently, many post-quantum cryptography schemes have been implemented on various hardware platforms in order to provide efficient solutions in cybersecurity services. As researchers and hardware developers focus primarily on designs providing small latency and requiring fewer hardware resources, their implementations could seldom omit protection techniques against various physical attacks. This paper studies potential attacks on the cryptography implementations that run on Field-Programmable Gate Array (FPGA) platforms. We mainly analyze how Post-Quantum Cryptography (PQC) implementations could be vulnerable on various platforms. Further, we aim at the FPGA-based implementations of National Institute of Standards and Technology (NIST)’s PQC competition finalists. Our study should present to developers the current overview of attacks and countermeasures that can be implemented on specific PQC schemes on FPGA platforms. Moreover, we present novel implementation of one universal countermeasure component and reveal additional resources that are needed.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20203 - Telecommunications

Projekt

<a href="/cs/project/VJ02010010" target="_blank" >VJ02010010: Nástroje pro verifikaci bezpečnosti kryptografických zařízení s využitím AI</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

ARES '22: Proceedings of the 17th International Conference on Availability, Reliability and Security

ISBN

978-1-4503-9670-7

ISSN

—

e-ISSN

—

Počet stran výsledku

9

Strana od-do

1-9

Název nakladatele

ACM

Místo vydání

Vienna, Austria

Místo konání akce

Vídeň

Datum konání akce

23. 8. 2022

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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