Design Space Exploration of Parallel Embedded Applications Based on Performance-Oriented Specifications

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36184" target="_blank" >RIV/00216305:26230/02:PU36184 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Design Space Exploration of Parallel Embedded Applications Based on Performance-Oriented Specifications

Popis výsledku v původním jazyce

The choice of HW/SW multiprocessor architecture for a specific embedded application is not an easy task due to many possible processing elements, type of their interconnection, various partitioning of the code and data and mapping them on processing elements. The paper addresses this issue and uses a single CSP-based simulation tool Transim for multiple architectures. Exploration of a vast design space for a generally heterogeneous network of processing elements is quick, because only first-order effectts can be considered. Variations in processor count, clock rate, link speed, bus bandwidth, cache line size, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on solution of large dense systems of linear equations in real time.

Název v anglickém jazyce

Design Space Exploration of Parallel Embedded Applications Based on Performance-Oriented Specifications

Popis výsledku anglicky

The choice of HW/SW multiprocessor architecture for a specific embedded application is not an easy task due to many possible processing elements, type of their interconnection, various partitioning of the code and data and mapping them on processing elements. The paper addresses this issue and uses a single CSP-based simulation tool Transim for multiple architectures. Exploration of a vast design space for a generally heterogeneous network of processing elements is quick, because only first-order effectts can be considered. Variations in processor count, clock rate, link speed, bus bandwidth, cache line size, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on solution of large dense systems of linear equations in real time.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F02%2F0503" target="_blank" >GA102/02/0503: Predikce a ladění paralelní výkonnosti</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2002

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the Joint Workshop on Formal Specifications of Computer-Based Systems

ISBN

1-85769-169-5

ISSN

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e-ISSN

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Počet stran výsledku

5

Strana od-do

71-75

Název nakladatele

University of Stirling

Místo vydání

Stirling

Místo konání akce

Lund

Datum konání akce

8. 4. 2002

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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