A Design Space Exploration Scheme for High-Level Synthesis Systems

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36194" target="_blank" >RIV/00216305:26230/02:PU36194 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

A Design Space Exploration Scheme for High-Level Synthesis Systems

Popis výsledku v původním jazyce

This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local explooration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock

Název v anglickém jazyce

A Design Space Exploration Scheme for High-Level Synthesis Systems

Popis výsledku anglicky

This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local explooration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formální postupy v diagnostice číslicových obvodů - verifikace testovatelného návrhu</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2002

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of 36th International Conference MOSIS '02 Modelling and Simulation of Systems

ISBN

80-85988-71-2

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

305-312

Název nakladatele

Neuveden

Místo vydání

Ostrava

Místo konání akce

Rožnov pod Radhoštěm

Datum konání akce

22. 4. 2002

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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