Fast Cycle-Accurate Interpreted Simulation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU86259" target="_blank" >RIV/00216305:26230/09:PU86259 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Fast Cycle-Accurate Interpreted Simulation

Popis výsledku v původním jazyce

&lt;!-- @page { margin: 0.79in } P { margin-bottom: 0.08in } --&gt; <p> The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hard

Název v anglickém jazyce

Fast Cycle-Accurate Interpreted Simulation

Popis výsledku anglicky

&lt;!-- @page { margin: 0.79in } P { margin-bottom: 0.08in } --&gt; <p> The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hard

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2009

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions

ISBN

978-0-7695-4000-9

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

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Název nakladatele

IEEE Computer Society Press

Místo vydání

Austin

Místo konání akce

Austin, Texas

Datum konání akce

7. 12. 2009

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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