Software Fault Tolerance: the Evaluation by Functional Verification

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU117053" target="_blank" >RIV/00216305:26230/15:PU117053 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/7302285" target="_blank" >https://ieeexplore.ieee.org/document/7302285</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2015.107" target="_blank" >10.1109/DSD.2015.107</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Software Fault Tolerance: the Evaluation by Functional Verification

Popis výsledku v původním jazyce

The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.

Název v anglickém jazyce

Software Fault Tolerance: the Evaluation by Functional Verification

Popis výsledku anglicky

The aim of this paper is to present a new approach in evaluating Software Fault Tolerance (SFT) methodologies. It is the way on how to ensure fault tolerance without any additional hardware as is common in frequently used Triple Modular Redundancy (TMR). As our research is focused on electromechanical systems which are commonly driven by processors or Multi Processors Systems on Chip (MPSoC) we decided to use the soft-core processor running on Field Programmable Gate Array (FPGA) as our experimental platform. The new approach uses Functional Verification for automation of the evaluation process. The functional verification environment is one of the important parts of the presented evaluation platform architecture. Programs generation for a processor, where SFT is applied, is also important. Experiments with the programs generator and fault injection are presented and goals for future work are identified on that basis.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 18th Euromicro Conference on Digital Systems Design

ISBN

978-1-4673-8035-5

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

284-287

Název nakladatele

IEEE Computer Society

Místo vydání

Funchal

Místo konání akce

Funchal

Datum konání akce

26. 8. 2015

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000382382300042