Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130698" target="_blank" >RIV/00216305:26230/18:PU130698 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11637" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11637</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/3205651.3205678" target="_blank" >10.1145/3205651.3205678</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria

Popis výsledku v původním jazyce

As a promising approach to the design of energy efficient circuits, approximate circuits and approximate circuit design methodologies have attracted a significant attention of researchers as well as industry. Compared to the traditional design methods, it has been demonstrated that evolutionary approaches are able to discover approximate circuits exhibiting a good trade-off between the energy consumption and circuit quality. In this work, evolutionary design of large approximate adders is addressed. In order to improve scalability, the quality of the candidate solutions is analysed using a formal approach based on Binary Decision Diagrams. Compared to the common approach based on a parallel circuit simulator, the proposed method is able to evaluate 2-3 orders of magnitude more generations.

Název v anglickém jazyce

Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria

Popis výsledku anglicky

As a promising approach to the design of energy efficient circuits, approximate circuits and approximate circuit design methodologies have attracted a significant attention of researchers as well as industry. Compared to the traditional design methods, it has been demonstrated that evolutionary approaches are able to discover approximate circuits exhibiting a good trade-off between the energy consumption and circuit quality. In this work, evolutionary design of large approximate adders is addressed. In order to improve scalability, the quality of the candidate solutions is analysed using a formal approach based on Binary Decision Diagrams. Compared to the common approach based on a parallel circuit simulator, the proposed method is able to evaluate 2-3 orders of magnitude more generations.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GA16-17538S" target="_blank" >GA16-17538S: Přibližná ekvivalence pro aproximativní počítání</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18)

ISBN

978-1-4503-5764-7

ISSN

—

e-ISSN

—

Počet stran výsledku

2

Strana od-do

294-295

Název nakladatele

Association for Computing Machinery

Místo vydání

Kyoto

Místo konání akce

Kyoto

Datum konání akce

15. 7. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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