Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130702" target="_blank" >RIV/00216305:26230/18:PU130702 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11752/" target="_blank" >https://www.fit.vut.cz/research/publication/11752/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/EWDTS.2018.8524631" target="_blank" >10.1109/EWDTS.2018.8524631</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis

Popis výsledku v původním jazyce

During the last decades, electronic systems became an important matter of controlling many critical processes. However, those critical processes often require increased reliability. This requirement puts pressure on system developers to make systems reliable. Because of ever growing chip-level integration, capabilities of electronic systems are expanding, and, thus, leading to more complex system architectures, significantly increasing the number of man-hours needed to develop such systems. Many people believe the solution is to move the development to a higher level of abstraction (e.g. an algorithm level) and use the so-called High-Level Synthesis (HLS) for this purpose. In this research, we aimed towards a decision, whether the usage of HLS impacts the resulting reliability properties of the system, and, thus, whether the HLS-generated system matches reliability properties of its corresponding VHDL-implemented version. We found out that, for the selected set of circuits, HLS performs better in terms of resource consumption, but, also, which we consider surprising, in terms of reliability. For the selected set, HLS achieved better reliability by 3.03 percentage points in contrast to the classical approach utilizing a traditional Hardware Description Language (HDL). In these experiments, no redundancy was intentionally inserted into benchmarking circuits.

Název v anglickém jazyce

Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis

Popis výsledku anglicky

During the last decades, electronic systems became an important matter of controlling many critical processes. However, those critical processes often require increased reliability. This requirement puts pressure on system developers to make systems reliable. Because of ever growing chip-level integration, capabilities of electronic systems are expanding, and, thus, leading to more complex system architectures, significantly increasing the number of man-hours needed to develop such systems. Many people believe the solution is to move the development to a higher level of abstraction (e.g. an algorithm level) and use the so-called High-Level Synthesis (HLS) for this purpose. In this research, we aimed towards a decision, whether the usage of HLS impacts the resulting reliability properties of the system, and, thus, whether the HLS-generated system matches reliability properties of its corresponding VHDL-implemented version. We found out that, for the selected set of circuits, HLS performs better in terms of resource consumption, but, also, which we consider surprising, in terms of reliability. For the selected set, HLS achieved better reliability by 3.03 percentage points in contrast to the classical approach utilizing a traditional Hardware Description Language (HDL). In these experiments, no redundancy was intentionally inserted into benchmarking circuits.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of IEEE East-West Design & Test Symposium

ISBN

978-1-5386-5710-2

ISSN

—

e-ISSN

—

Počet stran výsledku

7

Strana od-do

80-86

Název nakladatele

IEEE Computer Society

Místo vydání

Kazan

Místo konání akce

Kazan, Rusko

Datum konání akce

14. 9. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000517795800018