An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130752" target="_blank" >RIV/00216305:26230/18:PU130752 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11747/" target="_blank" >https://www.fit.vut.cz/research/publication/11747/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/EWDTS.2018.8524627" target="_blank" >10.1109/EWDTS.2018.8524627</a>

Jazyk výsledku

angličtina

Název v původním jazyce

An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller

Popis výsledku v původním jazyce

Field Programmable Gate Arrays (FPGAs) are becoming more popular in various areas. Single Event Upsets (SEUs) are faults caused by a charged particle in the configuration memory of SRAM-based FPGAs. Such a charged particle can cause incorrect behavior in the whole system. This problem becomes greater if such a system operates in an environment with increased radiation (e.g. space applications). Lots of techniques to harden FPGAs against faults exist and new ones are under investigation. One such technique is called Triple Modular Redundancy (TMR). It is important to evaluate these techniques on a real system with a real FPGA. An evaluation platform based on an artificial fault injection and a functional verification for testing fault tolerance methodologies is introduced in this paper. Parts of our experimental system are hardened by using TMR and its experimental evaluation is one of the main parts of this paper. We propose experiments with various fault injection strategies (single and multiple faults) and monitor its impact on both the electronic and mechanical parts of the experimental system.

Název v anglickém jazyce

An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller

Popis výsledku anglicky

Field Programmable Gate Arrays (FPGAs) are becoming more popular in various areas. Single Event Upsets (SEUs) are faults caused by a charged particle in the configuration memory of SRAM-based FPGAs. Such a charged particle can cause incorrect behavior in the whole system. This problem becomes greater if such a system operates in an environment with increased radiation (e.g. space applications). Lots of techniques to harden FPGAs against faults exist and new ones are under investigation. One such technique is called Triple Modular Redundancy (TMR). It is important to evaluate these techniques on a real system with a real FPGA. An evaluation platform based on an artificial fault injection and a functional verification for testing fault tolerance methodologies is introduced in this paper. Parts of our experimental system are hardened by using TMR and its experimental evaluation is one of the main parts of this paper. We propose experiments with various fault injection strategies (single and multiple faults) and monitor its impact on both the electronic and mechanical parts of the experimental system.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of IEEE East-West Design & Test Symposium

ISBN

978-1-5386-5710-2

ISSN

—

e-ISSN

—

Počet stran výsledku

7

Strana od-do

63-69

Název nakladatele

IEEE Computer Society

Místo vydání

Kazan

Místo konání akce

Kazan, Rusko

Datum konání akce

14. 9. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000517795800014