Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130755" target="_blank" >RIV/00216305:26230/18:PU130755 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11758/" target="_blank" >https://www.fit.vut.cz/research/publication/11758/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/EWDTS.2018.8524728" target="_blank" >10.1109/EWDTS.2018.8524728</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation

Popis výsledku v původním jazyce

Field Programmable Gate Arrays (FPGAs) are popular not only for their wide range of usage in embedded systems, however, they are susceptible to radiation effects. Charged particles cause the so-called Single Event Upsets (SEUs) in their configuration memory. SEUs can induce failure of the whole system. This problem is fundamental for space applications where sun radiation is more considerable than in the Earth. Two main approaches to SEU mitigation technique exist: fault masking and reparation. The most popular masking method is Triple Modular Redundancy (TMR). For the faults reparation, FPGA's capability of reconfiguration is used. It is possible to combine these approaches to obtain improved fault tolerant system. It is important to assess reliability rate of this system and, therefore, its estimation by a simulation is the main part of this paper. We propose evaluation environment which assesses the reliability of a TMR system with malfunction module reconfiguration depending on faults occurrence frequency and reconfiguration time necessary for fault reparation.

Název v anglickém jazyce

Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation

Popis výsledku anglicky

Field Programmable Gate Arrays (FPGAs) are popular not only for their wide range of usage in embedded systems, however, they are susceptible to radiation effects. Charged particles cause the so-called Single Event Upsets (SEUs) in their configuration memory. SEUs can induce failure of the whole system. This problem is fundamental for space applications where sun radiation is more considerable than in the Earth. Two main approaches to SEU mitigation technique exist: fault masking and reparation. The most popular masking method is Triple Modular Redundancy (TMR). For the faults reparation, FPGA's capability of reconfiguration is used. It is possible to combine these approaches to obtain improved fault tolerant system. It is important to assess reliability rate of this system and, therefore, its estimation by a simulation is the main part of this paper. We propose evaluation environment which assesses the reliability of a TMR system with malfunction module reconfiguration depending on faults occurrence frequency and reconfiguration time necessary for fault reparation.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of IEEE East-West Design & Test Symposium

ISBN

978-1-5386-5710-2

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

129-134

Název nakladatele

IEEE Computer Society

Místo vydání

Kazaň

Místo konání akce

Kazan, Rusko

Datum konání akce

14. 9. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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