Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU134152" target="_blank" >RIV/00216305:26230/19:PU134152 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11967/" target="_blank" >https://www.fit.vut.cz/research/publication/11967/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2019.00091" target="_blank" >10.1109/DSD.2019.00091</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

Popis výsledku v původním jazyce

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a processor is used in multiple designs. The goal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Název v anglickém jazyce

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study

Popis výsledku anglicky

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a processor is used in multiple designs. The goal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2019 22nd Euromicro Conference on Digital System Design

ISBN

978-1-7281-2861-0

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

597-600

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Kalithea

Místo konání akce

Athos Palace Hotel, Solinas, Kallithea 63077, Ch

Datum konání akce

28. 8. 2019

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000722275400082