Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU135818" target="_blank" >RIV/00216305:26230/20:PU135818 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/12080/" target="_blank" >https://www.fit.vut.cz/research/publication/12080/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/LASCAS45839.2020.9068977" target="_blank" >10.1109/LASCAS45839.2020.9068977</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks

Popis výsledku v původním jazyce

This research paper presents examination of the influences of faults on a control unit of smart electronic locks. A stepper motor is often used as an actuator of such smart locks and its motor controller is usually implemented in a processor. The aim of this paper is to examine the impact of faults occurring in the control processor. It should be noted that faults in such electronic systems can also be induced artificially, usually with ulterior motives. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. This allows us to use previously developed evaluation platform for fault tolerance testing. This platform allows us to monitor impact of faults both on electronic and mechanical parts of electro-mechanical system. In this paper, the evaluation of faults artificially injected in FPGA-based processor is proposed. Experiments with both single and multiple fault injections were held.

Název v anglickém jazyce

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks

Popis výsledku anglicky

This research paper presents examination of the influences of faults on a control unit of smart electronic locks. A stepper motor is often used as an actuator of such smart locks and its motor controller is usually implemented in a processor. The aim of this paper is to examine the impact of faults occurring in the control processor. It should be noted that faults in such electronic systems can also be induced artificially, usually with ulterior motives. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. This allows us to use previously developed evaluation platform for fault tolerance testing. This platform allows us to monitor impact of faults both on electronic and mechanical parts of electro-mechanical system. In this paper, the evaluation of faults artificially injected in FPGA-based processor is proposed. Experiments with both single and multiple fault injections were held.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)

ISBN

978-1-7281-3427-7

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

1-4

Název nakladatele

IEEE Circuits and Systems Society

Místo vydání

San José

Místo konání akce

Holiday Inn Hotel, Escazu, San José

Datum konání akce

25. 2. 2020

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

—