Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138618" target="_blank" >RIV/00216305:26230/20:PU138618 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/12256/" target="_blank" >https://www.fit.vut.cz/research/publication/12256/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD51259.2020.00110" target="_blank" >10.1109/DSD51259.2020.00110</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

Popis výsledku v původním jazyce

In this research paper, analysis of smart electronic lock behavior during presence of faults in its controller is examined. A typical smart electronic lock is composed of a controller unit, usually implemented in a processor, and the mechanical part, which may be for example a stepper motor. The goal of this research paper is to examine the consequences of failing controller running a partly hardened program, which we developed from the experiences we gained in our previous research. We implement the controller processor in Field Programmable Gate Array (FPGA) in order to inject faults into our components. This paper focuses on fault injection into occupied parts of Instruction Memory (IMEM) and Data Memory (DMEM). Moreover, permanent failures of the processor are simulated by fault injection into occupied Look-up Tables (LUTs) of the processor design on the FPGA. Our results show that the application of certain SW-implemented fault tolerance methods may, in opposite, degrade the hardness of the system. Our experiments imply that the IMEM is the most sensitive to fault injection, because there is no possibility for an eventual self repair. In the case of DMEM, erroneous values may be possibly repaired when the variable is rewritten back to the memory, slightly lowering the DMEM sensitivity to fault injections. The CPU itself is the least susceptible. Although faults are injected to the utilized contents only, for the CPU LUTs, a certain part of the logic may not be used to implement the required function.

Název v anglickém jazyce

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

Popis výsledku anglicky

In this research paper, analysis of smart electronic lock behavior during presence of faults in its controller is examined. A typical smart electronic lock is composed of a controller unit, usually implemented in a processor, and the mechanical part, which may be for example a stepper motor. The goal of this research paper is to examine the consequences of failing controller running a partly hardened program, which we developed from the experiences we gained in our previous research. We implement the controller processor in Field Programmable Gate Array (FPGA) in order to inject faults into our components. This paper focuses on fault injection into occupied parts of Instruction Memory (IMEM) and Data Memory (DMEM). Moreover, permanent failures of the processor are simulated by fault injection into occupied Look-up Tables (LUTs) of the processor design on the FPGA. Our results show that the application of certain SW-implemented fault tolerance methods may, in opposite, degrade the hardness of the system. Our experiments imply that the IMEM is the most sensitive to fault injection, because there is no possibility for an eventual self repair. In the case of DMEM, erroneous values may be possibly repaired when the variable is rewritten back to the memory, slightly lowering the DMEM sensitivity to fault injections. The CPU itself is the least susceptible. Although faults are injected to the utilized contents only, for the CPU LUTs, a certain part of the logic may not be used to implement the required function.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings - Euromicro Conference on Digital System Design, DSD 2020

ISBN

978-1-7281-9535-3

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

680-683

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Kranj

Místo konání akce

Portorož, Slovenia, Grand Hotel Bernardin

Datum konání akce

26. 8. 2020

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000630443300099