Optimization of the bond and etch-back silicon-on-insulator manufacturing processes

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F26821532%3A_____%2F13%3A%230000034" target="_blank" >RIV/26821532:_____/13:#0000034 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Optimization of the bond and etch-back silicon-on-insulator manufacturing processes

Popis výsledku v původním jazyce

We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the ?nal chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydro?uoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0

Název v anglickém jazyce

Optimization of the bond and etch-back silicon-on-insulator manufacturing processes

Popis výsledku anglicky

We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the ?nal chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydro?uoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JJ - Ostatní materiály

OECD FORD obor

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Projekt

<a href="/cs/project/TA01010078" target="_blank" >TA01010078: Struktury SOI pro pokročilé polovodičové aplikace</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Advanced Science, Engineering and Medicine

ISSN

2164-6627

e-ISSN

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Svazek periodika

5

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

5

Strana od-do

603-607

Kód UT WoS článku

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EID výsledku v databázi Scopus

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