Scan Based Circuits with Low Power Consumption

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F03%3A00000031" target="_blank" >RIV/46747885:24220/03:00000031 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Scan Based Circuits with Low Power Consumption

Popis výsledku v původním jazyce

An alternative parallel diagnostic access method called Random Access Scan (RAS) is not used in nowadays ICs because of more difficult routability. In spite of this fact the diagnostic methods with a random access to IC FFs are much less energy consumingThey have a disadvantage of higher hardware overhead. In order to maximize power savings and minimize the hardware overhead we have proposed a modified RAS diagnostic access method, which can be used together with the BS. The RAS cells, controlled by theBS TAP controller, replace internal scan chain FFs, which are known as sources of unwanted circuit activity during shifting test patterns. We have calculated the hardware overhead of the RAS circuits and the power dissipaWe have found that the proposedBS and RAS combination could be very useful for low power design and it does not introduce any additional delay in the functional path.

Název v anglickém jazyce

Scan Based Circuits with Low Power Consumption

Popis výsledku anglicky

An alternative parallel diagnostic access method called Random Access Scan (RAS) is not used in nowadays ICs because of more difficult routability. In spite of this fact the diagnostic methods with a random access to IC FFs are much less energy consumingThey have a disadvantage of higher hardware overhead. In order to maximize power savings and minimize the hardware overhead we have proposed a modified RAS diagnostic access method, which can be used together with the BS. The RAS cells, controlled by theBS TAP controller, replace internal scan chain FFs, which are known as sources of unwanted circuit activity during shifting test patterns. We have calculated the hardware overhead of the RAS circuits and the power dissipaWe have found that the proposedBS and RAS combination could be very useful for low power design and it does not introduce any additional delay in the functional path.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F01%2F0566" target="_blank" >GA102/01/0566: Metody optimalizace vestavěných diagnostických prostředků v integrovaných obvodech</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2003

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proc. of DDECS2003

ISBN

83-7143-557-6

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

227-232

Název nakladatele

Neuveden

Místo vydání

Neuveden

Místo konání akce

Poznan, Poland

Datum konání akce

14. 4. 2003

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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