On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F12%3A%230002015" target="_blank" >RIV/46747885:24220/12:#0002015 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.scopus.com" target="_blank" >http://www.scopus.com</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/FPL.2012.6339167" target="_blank" >10.1109/FPL.2012.6339167</a>

Jazyk výsledku

angličtina

Název v původním jazyce

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

Popis výsledku v původním jazyce

The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAsin time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. Thispaper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused b

Název v anglickém jazyce

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults (Stability of timing parameters of 45nm FPGA Spartan 6)

Popis výsledku anglicky

The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAsin time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. Thispaper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused b

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2012

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

ISBN

978-1-4673-2257-7

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

743-746

Název nakladatele

—

Místo vydání

—

Místo konání akce

Oslo

Datum konání akce

29. 8. 2012

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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