On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F14%3A%230003129" target="_blank" >RIV/46747885:24220/14:#0003129 - isvavai.cz</a>
Výsledek na webu
<a href="http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6841917&queryText%3DOn+reliability+enhancement+using+adaptive+core+voltage+scaling+and+variations+on+nanoscale+FPGAs" target="_blank" >http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6841917&queryText%3DOn+reliability+enhancement+using+adaptive+core+voltage+scaling+and+variations+on+nanoscale+FPGAs</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LATW.2014.6841917" target="_blank" >10.1109/LATW.2014.6841917</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs
Popis výsledku v původním jazyce
Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affectthe final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable
Název v anglickém jazyce
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs
Popis výsledku anglicky
Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affectthe final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
JC - Počítačový hardware a software
OECD FORD obor
—
Návaznosti výsledku
Projekt
<a href="/cs/project/LD13019" target="_blank" >LD13019: SPONA - Zvýšení spolehlivosti nanoscale obvodů</a><br>
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2014
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
15th IEEE Latin-American Test Workshop
ISBN
978-1-4799-4711-9
ISSN
—
e-ISSN
—
Počet stran výsledku
4
Strana od-do
—
Název nakladatele
IEEE Computer Society
Místo vydání
Brazil
Místo konání akce
Fortaleza
Datum konání akce
1. 1. 2014
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
—