Test-Data Compression with Low Number of Channels and Short Test Time

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Test-Data Compression with Low Number of Channels and Short Test Time

Popis výsledku v původním jazyce

The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompressionthat is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a waythat the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results

Název v anglickém jazyce

Test-Data Compression with Low Number of Channels and Short Test Time

Popis výsledku anglicky

The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompressionthat is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a waythat the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/LD13019" target="_blank" >LD13019: SPONA - Zvýšení spolehlivosti nanoscale obvodů</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS)

ISBN

978-1-4799-4558-0

ISSN

2334-3133

e-ISSN

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Počet stran výsledku

6

Strana od-do

104-109

Název nakladatele

IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA

Místo vydání

Warsaw, POLAND

Místo konání akce

Warsaw, POLAND

Datum konání akce

1. 1. 2014

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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