Test Pattern Decompression in Parallel Scan Chain Architecture

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F13%3A00215127" target="_blank" >RIV/68407700:21240/13:00215127 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DDECS.2013.6549820" target="_blank" >http://dx.doi.org/10.1109/DDECS.2013.6549820</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2013.6549820" target="_blank" >10.1109/DDECS.2013.6549820</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Test Pattern Decompression in Parallel Scan Chain Architecture

Popis výsledku v původním jazyce

The paper presents a test-data volume-compression method which reduces test time and hardware overhead by test pattern broadcast into parallel scan chains. The proposed hardware enables efficient test pattern decompression and test response compaction. It uses a XOR-less structure instead of ring generators for test pattern decompression. Decompressed test vectors are obtained from the previously generated ones by simple shift operations only. The compression algorithm can search in a wider pattern space when finding the best fitting decompressor seed sequence because of this arrangement. The faults of basic gates can be covered by the patterns easily obtained in the decompressor during several clock cycles as a majority of faults can be tested by patterns that differ in a few shift operations only. The paper describes a test pattern decompressor hardware including its controller. The decompressor reduces the number of flip-flops containing information about previously generated patter

Název v anglickém jazyce

Test Pattern Decompression in Parallel Scan Chain Architecture

Popis výsledku anglicky

The paper presents a test-data volume-compression method which reduces test time and hardware overhead by test pattern broadcast into parallel scan chains. The proposed hardware enables efficient test pattern decompression and test response compaction. It uses a XOR-less structure instead of ring generators for test pattern decompression. Decompressed test vectors are obtained from the previously generated ones by simple shift operations only. The compression algorithm can search in a wider pattern space when finding the best fitting decompressor seed sequence because of this arrangement. The faults of basic gates can be covered by the patterns easily obtained in the decompressor during several clock cycles as a majority of faults can be tested by patterns that differ in a few shift operations only. The paper describes a test pattern decompressor hardware including its controller. The decompressor reduces the number of flip-flops containing information about previously generated patter

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

ISBN

978-1-4673-6135-4

ISSN

—

e-ISSN

—

Počet stran výsledku

5

Strana od-do

219-223

Název nakladatele

IEEE

Místo vydání

New York

Místo konání akce

Karlovy Vary

Datum konání akce

8. 4. 2013

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

000325168900046