Optimization of PCB Design Assembly Using Yield Prediction

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Optimization of PCB Design Assembly Using Yield Prediction

Popis výsledku v původním jazyce

The paper deals with optimization of printed circuit board design using yield prediction. Yield prediction of PCB assembly process can be obtained from the below presented yield model. The model is based on a combination of elements from two most used yield prediction methodologies, namely: process yield and board design yield. Due to PCB assembly process yield prediction is possible not only to assist the manufacturers in determining reliable estimates of production capabilities, but also to optimize PCB design process. Through the use of sensitivity analysis can be determined the effect that each component package has on the manufacturing yield. The component packages having the biggest influence on the manufacturing yield loss represent potential failure areas. Due to this information is possible to optimize PCB design before the start of mass production in order to minimize or even to eliminate these problematic component packages.

Název v anglickém jazyce

Optimization of PCB Design Assembly Using Yield Prediction

Popis výsledku anglicky

The paper deals with optimization of printed circuit board design using yield prediction. Yield prediction of PCB assembly process can be obtained from the below presented yield model. The model is based on a combination of elements from two most used yield prediction methodologies, namely: process yield and board design yield. Due to PCB assembly process yield prediction is possible not only to assist the manufacturers in determining reliable estimates of production capabilities, but also to optimize PCB design process. Through the use of sensitivity analysis can be determined the effect that each component package has on the manufacturing yield. The component packages having the biggest influence on the manufacturing yield loss represent potential failure areas. Due to this information is possible to optimize PCB design before the start of mass production in order to minimize or even to eliminate these problematic component packages.

Druh

D - Stať ve sborníku

CEP obor

JS - Řízení spolehlivosti a kvality, zkušebnictví

OECD FORD obor

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Projekt

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Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2008

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

ISEE 2008

ISBN

978-1-4244-3973-7

ISSN

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e-ISSN

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Počet stran výsledku

5

Strana od-do

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Název nakladatele

IEEE

Místo vydání

New York

Místo konání akce

Budapešť

Datum konání akce

1. 1. 2008

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000272337900069