P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F16%3A10130695" target="_blank" >RIV/63839172:_____/16:10130695 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21240/16:00301150

Výsledek na webu

<a href="http://dx.doi.org/10.1109/FCCM.2016.46" target="_blank" >http://dx.doi.org/10.1109/FCCM.2016.46</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/FCCM.2016.46" target="_blank" >10.1109/FCCM.2016.46</a>

Jazyk výsledku

angličtina

Název v původním jazyce

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Popis výsledku v původním jazyce

Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be run-time tailored for the needs of particular applications from various domains. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator. The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at line rate on a Xilinx Virtex-7 FPGA. The approach can be used not only in switches, but also in other appliances, such as application accelerators and smart NICs. We compare the generated output to a hand-written parser to show that the price for configurability is only a slightly larger and slower circuit.

Název v anglickém jazyce

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Popis výsledku anglicky

Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be run-time tailored for the needs of particular applications from various domains. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator. The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at line rate on a Xilinx Virtex-7 FPGA. The approach can be used not only in switches, but also in other appliances, such as application accelerators and smart NICs. We compare the generated output to a hand-written parser to show that the price for configurability is only a slightly larger and slower circuit.

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

—

Projekt

—

Návaznosti

R - Projekt Ramcoveho programu EK

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines

ISBN

978-1-5090-2356-1

ISSN

—

e-ISSN

—

Počet stran výsledku

8

Strana od-do

148-155

Název nakladatele

IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA

Místo vydání

Washington, DC, USA

Místo konání akce

Washington, DC, USA

Datum konání akce

1. 5. 2016

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000389602200037