Automatic Generation of 100 Gbps Packet Parsers from P4 Description

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00235676" target="_blank" >RIV/68407700:21240/15:00235676 - isvavai.cz</a>

Výsledek na webu

<a href="http://h2rc.cse.sc.edu/h2rc-p2.pdf" target="_blank" >http://h2rc.cse.sc.edu/h2rc-p2.pdf</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Automatic Generation of 100 Gbps Packet Parsers from P4 Description

Popis výsledku v původním jazyce

Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be run-time tailored for the needs of particular applications from various domains, such as HPC. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator.The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at

Název v anglickém jazyce

Automatic Generation of 100 Gbps Packet Parsers from P4 Description

Popis výsledku anglicky

Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be run-time tailored for the needs of particular applications from various domains, such as HPC. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator.The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at

Druh

O - Ostatní výsledky

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

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Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů