Line rate programmable packet processing in 100Gb networks

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F17%3A10132922" target="_blank" >RIV/63839172:_____/17:10132922 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/8056835/" target="_blank" >http://ieeexplore.ieee.org/document/8056835/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.23919/FPL.2017.8056835" target="_blank" >10.23919/FPL.2017.8056835</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Line rate programmable packet processing in 100Gb networks

Popis výsledku v původním jazyce

The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. The results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

Název v anglickém jazyce

Line rate programmable packet processing in 100Gb networks

Popis výsledku anglicky

The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. The results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

Druh

O - Ostatní výsledky

CEP obor

—

OECD FORD obor

10200 - Computer and information sciences

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů