Verification of Generated RTL from P4 Source Code

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133074" target="_blank" >RIV/63839172:_____/18:10133074 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8526853&isnumber=8526788" target="_blank" >https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8526853&isnumber=8526788</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICNP.2018.00065" target="_blank" >10.1109/ICNP.2018.00065</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Verification of Generated RTL from P4 Source Code

Popis výsledku v původním jazyce

The P4 is a general and platform agnostic language for the description of packet processing functionality. So far it is being supported by a number of technology companies which provided a way for programming of their devices using the P4 language. One of possible platforms is a SmartNIC - a Field Programmable Gate Array (FPGA) device which connects flexibility with high performance into a compact package. FPGA circuits are typically programmed in a Hardware Description Language (HDL) like VHDL or Verilog. These languages are hard to learn for novices and the development of a network device is very time consuming. Therefore, researchers around the world are finding a way how to automate the translation process from P4 to HDL language because such approach allows easy and fast programming of FPGA SmartNICs to a big audience of network experts. There are currently available three main compilers for the translation of P4 source to HDL - SDNet P4FPGA and P4-to-VHDL. In our best knowledge, all mentioned compilers don&apos;t provide any automated test environment which can be used repeatedly for different P4 programs. In other words, the verification environment has to be written by hand for each P4 program. Our work demonstrates a possible solution for automated verification of generated Register Transfer Level (RTL) description of a packet processing device from provided P4 source code.

Název v anglickém jazyce

Verification of Generated RTL from P4 Source Code

Popis výsledku anglicky

The P4 is a general and platform agnostic language for the description of packet processing functionality. So far it is being supported by a number of technology companies which provided a way for programming of their devices using the P4 language. One of possible platforms is a SmartNIC - a Field Programmable Gate Array (FPGA) device which connects flexibility with high performance into a compact package. FPGA circuits are typically programmed in a Hardware Description Language (HDL) like VHDL or Verilog. These languages are hard to learn for novices and the development of a network device is very time consuming. Therefore, researchers around the world are finding a way how to automate the translation process from P4 to HDL language because such approach allows easy and fast programming of FPGA SmartNICs to a big audience of network experts. There are currently available three main compilers for the translation of P4 source to HDL - SDNet P4FPGA and P4-to-VHDL. In our best knowledge, all mentioned compilers don&apos;t provide any automated test environment which can be used repeatedly for different P4 programs. In other words, the verification environment has to be written by hand for each P4 program. Our work demonstrates a possible solution for automated verification of generated Register Transfer Level (RTL) description of a packet processing device from provided P4 source code.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/TH02010214" target="_blank" >TH02010214: Platforma pro akceleraci virtualizace funkcí sítě</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2018 IEEE 26th International Conference on Network Protocols

ISBN

978-1-5386-6043-0

ISSN

1092-1648

e-ISSN

neuvedeno

Počet stran výsledku

2

Strana od-do

444-445

Název nakladatele

IEEE Computer Society

Místo vydání

Los Alamitos

Místo konání akce

Cambridge, Anglie

Datum konání akce

25. 9. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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