Occurrence of Voids in Soldered Joints for Electrical Engineering

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21220%2F24%3A00378838" target="_blank" >RIV/68407700:21220/24:00378838 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21230/24:00378838

Výsledek na webu

<a href="https://doi.org/10.1109/ISSE61612.2024.10603930" target="_blank" >https://doi.org/10.1109/ISSE61612.2024.10603930</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISSE61612.2024.10603930" target="_blank" >10.1109/ISSE61612.2024.10603930</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Occurrence of Voids in Soldered Joints for Electrical Engineering

Popis výsledku v původním jazyce

The research focuses on the occurrence of voids in soldered joints in the field of electrical engineering. The main goal was to analyze the occurrence of voids in soldered joints and to propose effective strategies to minimize this defect. BGA chips mounted on 10-layer PCBs were chosen as test samples. The current work focuses on defining production conditions and analyzing X-ray images. The analysis results implies that the parameters were chosen correctly and the acceptability criteria according to the ECSS-Q-ST-70-61C standard (defining soldering qualification for the space industry) were met with a margin, allowing for further types of tests such as vibration test and temperature cycling.

Název v anglickém jazyce

Occurrence of Voids in Soldered Joints for Electrical Engineering

Popis výsledku anglicky

The research focuses on the occurrence of voids in soldered joints in the field of electrical engineering. The main goal was to analyze the occurrence of voids in soldered joints and to propose effective strategies to minimize this defect. BGA chips mounted on 10-layer PCBs were chosen as test samples. The current work focuses on defining production conditions and analyzing X-ray images. The analysis results implies that the parameters were chosen correctly and the acceptability criteria according to the ECSS-Q-ST-70-61C standard (defining soldering qualification for the space industry) were met with a margin, allowing for further types of tests such as vibration test and temperature cycling.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2024 47th International Spring Seminar on Electronics Technology (ISSE)

ISBN

979-8-3503-8548-9

ISSN

2161-2536

e-ISSN

—

Počet stran výsledku

5

Strana od-do

—

Název nakladatele

IEEE Press

Místo vydání

New York

Místo konání akce

Praha

Datum konání akce

15. 5. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001283808200050