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Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03108031" target="_blank" >RIV/68407700:21230/05:03108031 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Output Grouping-Based Decomposition of Logic Functions

Popis výsledku v původním jazyce

We present a method allowing us to determine the grouping of the outputs of the multi output Boolean logic function for a single-level partitioning and minimization. Some kind of decomposition is often needed during the synthesis of logic circuits and the subsequent mapping onto technology. Sometimes a circuit has to be divided into several stand-alone parts, among its outputs, or possibly its inputs. It could be a case of a design targeted into PLAs, GALs, or any other monolithic components having a limited number of inputs and/or outputs. We propose a methodology to determine the way how the original circuit has to be partitioned into several parts of an arbitrary size, in order to reduce the complexity of the individual parts. The method is based onour FC-Min minimizer, even when no Boolean minimization has to be involved here. The efficiency of the method is demonstrated on the standard MCNC benchmarks.

Název v anglickém jazyce

Output Grouping-Based Decomposition of Logic Functions

Popis výsledku anglicky

We present a method allowing us to determine the grouping of the outputs of the multi output Boolean logic function for a single-level partitioning and minimization. Some kind of decomposition is often needed during the synthesis of logic circuits and the subsequent mapping onto technology. Sometimes a circuit has to be divided into several stand-alone parts, among its outputs, or possibly its inputs. It could be a case of a design targeted into PLAs, GALs, or any other monolithic components having a limited number of inputs and/or outputs. We propose a methodology to determine the way how the original circuit has to be partitioned into several parts of an arbitrary size, in order to reduce the complexity of the individual parts. The method is based onour FC-Min minimizer, even when no Boolean minimization has to be involved here. The efficiency of the method is demonstrated on the standard MCNC benchmarks.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Návrh vysoce spolehlivých řídících systémů pomocí dynamicky rekonfigurovatelných obvodů FPGA</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2005

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

ISBN

963 9364 48 7

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

137-144

Název nakladatele

University of Western Hungary

Místo vydání

Sopron

Místo konání akce

Sopron

Datum konání akce

13. 4. 2005

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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