A cyclic scheduling problem with an undetermined number of parallel identical processors

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F11%3A00157624" target="_blank" >RIV/68407700:21230/11:00157624 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/26074699:_____/11:#0000011

Výsledek na webu

<a href="http://www.springerlink.com/content/g3011566831157l8/" target="_blank" >http://www.springerlink.com/content/g3011566831157l8/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/s10589-009-9239-4" target="_blank" >10.1007/s10589-009-9239-4</a>

Jazyk výsledku

angličtina

Název v původním jazyce

A cyclic scheduling problem with an undetermined number of parallel identical processors

Popis výsledku v původním jazyce

This paper presents two integer linear programming (ILP) models for cyclic scheduling of tasks with unit/general processing time. Our work is motivated by digital signal processing (DSP) applications on FPGAs (Field-Programmable Gate Arrays)-hardware architectures hosting several sets of identical arithmetic units. These hardware units can be formalized as dedicated sets of parallel identical processors. We propose a method to find an optimal periodic schedule of DSP algorithms on such architectures where the number of available arithmetic units must be determined during scheduling with respect to the capacity of the FPGA circuit. The emphasis is put on the efficiency of the ILP models. We show the advantages of our models in comparison with common ILPmodels on benchmarks and randomly generated instances.

Název v anglickém jazyce

A cyclic scheduling problem with an undetermined number of parallel identical processors

Popis výsledku anglicky

This paper presents two integer linear programming (ILP) models for cyclic scheduling of tasks with unit/general processing time. Our work is motivated by digital signal processing (DSP) applications on FPGAs (Field-Programmable Gate Arrays)-hardware architectures hosting several sets of identical arithmetic units. These hardware units can be formalized as dedicated sets of parallel identical processors. We propose a method to find an optimal periodic schedule of DSP algorithms on such architectures where the number of available arithmetic units must be determined during scheduling with respect to the capacity of the FPGA circuit. The emphasis is put on the efficiency of the ILP models. We show the advantages of our models in comparison with common ILPmodels on benchmarks and randomly generated instances.

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

BB - Aplikovaná statistika, operační výzkum

OECD FORD obor

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Projekt

<a href="/cs/project/2C06017" target="_blank" >2C06017: Internetová platforma a algoritmy pro rozvrhování a optimalizaci</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2011

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Computational Optimization and Applications

ISSN

0926-6003

e-ISSN

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Svazek periodika

48

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

20

Strana od-do

71-90

Kód UT WoS článku

000286717700005

EID výsledku v databázi Scopus

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