Towards predictable execution model on ARM-based heterogeneous platforms

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F17%3A00315129" target="_blank" >RIV/68407700:21230/17:00315129 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/ISIE.2017.8001432" target="_blank" >http://dx.doi.org/10.1109/ISIE.2017.8001432</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISIE.2017.8001432" target="_blank" >10.1109/ISIE.2017.8001432</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Towards predictable execution model on ARM-based heterogeneous platforms

Popis výsledku v původním jazyce

Many today's real-time applications, such as Advanced Driver Assistant Systems (ADAS), demand both high computing power and safety guarantees. High computing power can be easily delivered by, now ubiquitous, multi-core CPUs or by a heterogeneous system with a multi-core CPU and a parallel accelerator such as a GPU. Reaching the required safety level in such a system is by far more difficult because the commercial-of-the-shelf (COTS) high-performance platforms contain many shared resources (e.g. main memory) with arbiters not designed to provide real-time guarantees. A promising approach to address this problem, known as PRedictable Execution Model (PREM), was introduced by Pellizzoni et al. [1]. We are interested in applying PREM to ARM-based heterogeneous platforms, but so far, all PREM-related work has been done on x86 or PowerPC. In this paper, we introduce several building blocks that are needed for implementing PREM on NVIDIA Tegra X1 platform. We propose a modification of the MemGuard tool to be practically usable on ARM platforms. We also analyse a throttling mechanism of Tegra X1 memory controller, that allows controlling memory bandwidth of non-CPU clients such as the GPU. We show that this mechanism can be used to make the execution time of CPU tasks more predictable.

Název v anglickém jazyce

Towards predictable execution model on ARM-based heterogeneous platforms

Popis výsledku anglicky

Many today's real-time applications, such as Advanced Driver Assistant Systems (ADAS), demand both high computing power and safety guarantees. High computing power can be easily delivered by, now ubiquitous, multi-core CPUs or by a heterogeneous system with a multi-core CPU and a parallel accelerator such as a GPU. Reaching the required safety level in such a system is by far more difficult because the commercial-of-the-shelf (COTS) high-performance platforms contain many shared resources (e.g. main memory) with arbiters not designed to provide real-time guarantees. A promising approach to address this problem, known as PRedictable Execution Model (PREM), was introduced by Pellizzoni et al. [1]. We are interested in applying PREM to ARM-based heterogeneous platforms, but so far, all PREM-related work has been done on x86 or PowerPC. In this paper, we introduce several building blocks that are needed for implementing PREM on NVIDIA Tegra X1 platform. We propose a modification of the MemGuard tool to be practically usable on ARM platforms. We also analyse a throttling mechanism of Tegra X1 memory controller, that allows controlling memory bandwidth of non-CPU clients such as the GPU. We show that this mechanism can be used to make the execution time of CPU tasks more predictable.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 26th IEEE International Symposium on Industrial Electronics

ISBN

978-1-5090-1412-5

ISSN

2163-5137

e-ISSN

—

Počet stran výsledku

6

Strana od-do

1297-1302

Název nakladatele

IEEE

Místo vydání

Piscataway, NJ

Místo konání akce

ISIE 2017

Datum konání akce

18. 7. 2017

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000426794000204