Real-Time FPGA-Based Detection of Speeded-Up Robust Features Using Separable Convolution

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F18%3A00315459" target="_blank" >RIV/68407700:21230/18:00315459 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/8074797/" target="_blank" >http://ieeexplore.ieee.org/document/8074797/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TII.2017.2764485" target="_blank" >10.1109/TII.2017.2764485</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Real-Time FPGA-Based Detection of Speeded-Up Robust Features Using Separable Convolution

Popis výsledku v původním jazyce

In this paper, we propose a novel architecture for efficient detection of Speeded Up Robust Features (SURF) for Field-programmable gate array (FPGA). The main benefits of the proposed architecture are in real-time low-latency performance and scalability. The proposed solution provides a significant acceleration of salient points extraction which is fundamental image processing technique for vision-based methods including the simultaneous localization and mapping (SLAM). Based on the presented practical results, the proposed architecture is capable of processing streaming image data at the rate of 140 Megapixels per second which roughly scales from the 640x480@420fps up to 1920x1080@60fps video streams on a low-end, low-cost FPGA solution (Cyclone V). Moreover, the proposed feature detection utilizes only about 20% of logic elements of the FPGA which supports further parallel processing of multiple inputs.

Název v anglickém jazyce

Real-Time FPGA-Based Detection of Speeded-Up Robust Features Using Separable Convolution

Popis výsledku anglicky

In this paper, we propose a novel architecture for efficient detection of Speeded Up Robust Features (SURF) for Field-programmable gate array (FPGA). The main benefits of the proposed architecture are in real-time low-latency performance and scalability. The proposed solution provides a significant acceleration of salient points extraction which is fundamental image processing technique for vision-based methods including the simultaneous localization and mapping (SLAM). Based on the presented practical results, the proposed architecture is capable of processing streaming image data at the rate of 140 Megapixels per second which roughly scales from the 640x480@420fps up to 1920x1080@60fps video streams on a low-end, low-cost FPGA solution (Cyclone V). Moreover, the proposed feature detection utilizes only about 20% of logic elements of the FPGA which supports further parallel processing of multiple inputs.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GJ15-09600Y" target="_blank" >GJ15-09600Y: Adaptivní plánování v úlohách autonomního sběru dat v nestrukturovaném prostředí</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS

ISSN

1551-3203

e-ISSN

1941-0050

Svazek periodika

14

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

9

Strana od-do

1155-1163

Kód UT WoS článku

000426700600034

EID výsledku v databázi Scopus

2-s2.0-85032283396