Low-Latency Image Processing for Vision-Based Navigation Systems

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00306999" target="_blank" >RIV/68407700:21230/16:00306999 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/7487207/" target="_blank" >http://ieeexplore.ieee.org/document/7487207/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICRA.2016.7487207" target="_blank" >10.1109/ICRA.2016.7487207</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Low-Latency Image Processing for Vision-Based Navigation Systems

Popis výsledku v původním jazyce

This paper concerns a problem of the latency reduction in the vision-based mobile robot navigation, which is considered as the crucial system property to determine a control command based on visual data in practical deployments of mobile robots. The problem is addressed by a processor centric FPGA-based System-on-Chip design allowing power and computationally efficient on-line image processing. The proposed architecture is considered in an autonomous vision-based navigation with a teach-and-repeat algorithm based on detection and tracking of image salient points. The architecture has been evaluated and compared with a CPU-based solution on different platforms and the results indicate that the proposed FPGA-based implementation outperforms pure CPU solutions in the overall latency, speed, and power consumption.

Název v anglickém jazyce

Low-Latency Image Processing for Vision-Based Navigation Systems

Popis výsledku anglicky

This paper concerns a problem of the latency reduction in the vision-based mobile robot navigation, which is considered as the crucial system property to determine a control command based on visual data in practical deployments of mobile robots. The problem is addressed by a processor centric FPGA-based System-on-Chip design allowing power and computationally efficient on-line image processing. The proposed architecture is considered in an autonomous vision-based navigation with a teach-and-repeat algorithm based on detection and tracking of image salient points. The architecture has been evaluated and compared with a CPU-based solution on different platforms and the results indicate that the proposed FPGA-based implementation outperforms pure CPU solutions in the overall latency, speed, and power consumption.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

<a href="/cs/project/GJ15-09600Y" target="_blank" >GJ15-09600Y: Adaptivní plánování v úlohách autonomního sběru dat v nestrukturovaném prostředí</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

IEEE International Conference on Robotics and Automation

ISBN

978-1-4673-8026-3

ISSN

1050-4729

e-ISSN

—

Počet stran výsledku

6

Strana od-do

781-786

Název nakladatele

Institute of Electrical and Electronics Engineers Inc.

Místo vydání

Budapešť

Místo konání akce

Stockholm

Datum konání akce

16. 5. 2016

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000389516200098