Comparison of MOSFET Gate Waffle Patterns Based on Specific On-Resistance

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F19%3A00334199" target="_blank" >RIV/68407700:21230/19:00334199 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.13164/re.2019.0598" target="_blank" >https://doi.org/10.13164/re.2019.0598</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.13164/re.2019.0598" target="_blank" >10.13164/re.2019.0598</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Comparison of MOSFET Gate Waffle Patterns Based on Specific On-Resistance

Popis výsledku v původním jazyce

This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, until today no precise model considering segmentation of MOSFETs with waffle gate patterns, due to bulk connections, has been proposed. Two different MOSFET topologies with gate waffle patterns have been investigated and compared with the same on-resistance of a standard MOSFET with finger gate pattern. The first one with diagonal metal interconnections allows reaching more than 40% area reduction. The second MOSFET with the simpler orthogonal metal interconnections allows saving more than 20% area. Moreover, new models defining conditions where segmented power MOSFETs with waffle gate patterns occupy less area than the standard MOSFET with finger gate pattern, have been introduced.

Název v anglickém jazyce

Comparison of MOSFET Gate Waffle Patterns Based on Specific On-Resistance

Popis výsledku anglicky

This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, until today no precise model considering segmentation of MOSFETs with waffle gate patterns, due to bulk connections, has been proposed. Two different MOSFET topologies with gate waffle patterns have been investigated and compared with the same on-resistance of a standard MOSFET with finger gate pattern. The first one with diagonal metal interconnections allows reaching more than 40% area reduction. The second MOSFET with the simpler orthogonal metal interconnections allows saving more than 20% area. Moreover, new models defining conditions where segmented power MOSFETs with waffle gate patterns occupy less area than the standard MOSFET with finger gate pattern, have been introduced.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Radioengineering

ISSN

1210-2512

e-ISSN

—

Svazek periodika

28

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

CZ - Česká republika

Počet stran výsledku

12

Strana od-do

598-609

Kód UT WoS článku

000485877700015

EID výsledku v databázi Scopus

2-s2.0-85076701209