Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F12%3A00197211" target="_blank" >RIV/68407700:21240/12:00197211 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/ICECS.2012.6463632" target="_blank" >http://dx.doi.org/10.1109/ICECS.2012.6463632</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICECS.2012.6463632" target="_blank" >10.1109/ICECS.2012.6463632</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA

Popis výsledku v původním jazyce

The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture dependingon the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension.

Název v anglickém jazyce

Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA

Popis výsledku anglicky

The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture dependingon the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension.

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

<a href="/cs/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Studium vlastností residuální aritmetiky pro řešení soustav lineárních rovnic</a><br>

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2012

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

ISBN

978-1-4673-1261-5

ISSN

—

e-ISSN

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Počet stran výsledku

4

Strana od-do

689-692

Název nakladatele

IEEE Circuits and Systems Society

Místo vydání

Monterey

Místo konání akce

Seville

Datum konání akce

9. 12. 2012

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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