Techniques for SAT-Based Constrained Test Pattern Generation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F13%3A00203004" target="_blank" >RIV/68407700:21240/13:00203004 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1016/j.micpro.2012.09.010" target="_blank" >http://dx.doi.org/10.1016/j.micpro.2012.09.010</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2012.09.010" target="_blank" >10.1016/j.micpro.2012.09.010</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Techniques for SAT-Based Constrained Test Pattern Generation

Popis výsledku v původním jazyce

Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefitfrom an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS?85, ?89 and ITC?99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SAT-based tools

Název v anglickém jazyce

Techniques for SAT-Based Constrained Test Pattern Generation

Popis výsledku anglicky

Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefitfrom an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS?85, ?89 and ITC?99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SAT-based tools

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

—

Svazek periodika

37

Číslo periodika v rámci svazku

2

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

11

Strana od-do

185-195

Kód UT WoS článku

000317166000007

EID výsledku v databázi Scopus

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