FPGA Accelerated Change-Point Detection Method for 100 Gb/s Networks

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00221356" target="_blank" >RIV/68407700:21240/14:00221356 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/63839172:_____/14:10130397

Výsledek na webu

<a href="http://www.memics.cz/2014/download/memics2014-proceedings.pdf" target="_blank" >http://www.memics.cz/2014/download/memics2014-proceedings.pdf</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

FPGA Accelerated Change-Point Detection Method for 100 Gb/s Networks

Popis výsledku v původním jazyce

The aim of this paper is a hardware realization of a statistical anomaly detection method as a part of high-speed monitoring probe for computer networks. The sequential Non-Parametric Cumulative Sum (NP-CUSUM) procedure is the detection method of our choice and we use an FPGA based accelerator card as the target platform. For rapid detection algorithm development, a high-level synthesis (HLS) approach is applied. Furthermore, we combine HLS with the usage of Software Defined Monitoring (SDM) framework on the monitoring probe, which enables easy deployment of various hardware-accelerated monitoring applications into high-speed networks. Our implementation of NP-CUSUM algorithm serves as hardware plug-in for SDM and realizes the detection of network attacks and anomalies directly in FPGA. Additionally, the parallel nature of the FPGA technology allows us to realize multiple different detections simultaneously without any losses in throughput. Our experimental results show the feasibility

Název v anglickém jazyce

FPGA Accelerated Change-Point Detection Method for 100 Gb/s Networks

Popis výsledku anglicky

The aim of this paper is a hardware realization of a statistical anomaly detection method as a part of high-speed monitoring probe for computer networks. The sequential Non-Parametric Cumulative Sum (NP-CUSUM) procedure is the detection method of our choice and we use an FPGA based accelerator card as the target platform. For rapid detection algorithm development, a high-level synthesis (HLS) approach is applied. Furthermore, we combine HLS with the usage of Software Defined Monitoring (SDM) framework on the monitoring probe, which enables easy deployment of various hardware-accelerated monitoring applications into high-speed networks. Our implementation of NP-CUSUM algorithm serves as hardware plug-in for SDM and realizes the detection of network attacks and anomalies directly in FPGA. Additionally, the parallel nature of the FPGA technology allows us to realize multiple different detections simultaneously without any losses in throughput. Our experimental results show the feasibility

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

<a href="/cs/project/LM2010005" target="_blank" >LM2010005: Velká infrastruktura CESNET</a><br>

Návaznosti

V - Vyzkumna aktivita podporovana z jinych verejnych zdroju

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

MEMICS proceedings

ISBN

978-80-214-5022-6

ISSN

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e-ISSN

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Počet stran výsledku

12

Strana od-do

40-51

Název nakladatele

NOVPRESS

Místo vydání

Brno

Místo konání akce

Telč

Datum konání akce

17. 10. 2014

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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