Enhanced duplication method with TMR-like masking abilities

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00301329" target="_blank" >RIV/68407700:21240/16:00301329 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DSD.2016.91" target="_blank" >http://dx.doi.org/10.1109/DSD.2016.91</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2016.91" target="_blank" >10.1109/DSD.2016.91</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Enhanced duplication method with TMR-like masking abilities

Popis výsledku v původním jazyce

This paper proposes a method improving the faultcoverage capabilities of Field Programmable Gate Array (FPGA) designs. Faults are mostly single event upsets (SEUs) in the configuration memory of SRAM-based FPGAs and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs – the Look-Up Table (LUT) with two outputs. The Parity Waterfall method (based on a cascade – waterfall – of several waves of inner parity generating the final parity of outputs of the whole circuit) presented in our previous paper has been encapsulated into a Duplication scheme in this paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy (TMR) method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method in comparison with TMR – the proposed method has a lower relative overhead and requires a lower number of inputs and outputs.

Název v anglickém jazyce

Enhanced duplication method with TMR-like masking abilities

Popis výsledku anglicky

This paper proposes a method improving the faultcoverage capabilities of Field Programmable Gate Array (FPGA) designs. Faults are mostly single event upsets (SEUs) in the configuration memory of SRAM-based FPGAs and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs – the Look-Up Table (LUT) with two outputs. The Parity Waterfall method (based on a cascade – waterfall – of several waves of inner parity generating the final parity of outputs of the whole circuit) presented in our previous paper has been encapsulated into a Duplication scheme in this paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy (TMR) method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method in comparison with TMR – the proposed method has a lower relative overhead and requires a lower number of inputs and outputs.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016

ISBN

978-1-5090-2816-0

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

690-693

Název nakladatele

IEEE Computer Soc.

Místo vydání

Los Alamitos, CA

Místo konání akce

Limassol, Cyprus

Datum konání akce

31. 8. 2016

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000386638800095