A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00303813" target="_blank" >RIV/68407700:21240/16:00303813 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/7857146/" target="_blank" >http://ieeexplore.ieee.org/document/7857146/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ReConFig.2016.7857146" target="_blank" >10.1109/ReConFig.2016.7857146</a>

Jazyk výsledku

angličtina

Název v původním jazyce

A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time

Popis výsledku v původním jazyce

This paper describes analysis and implementation of a new method for maintaining valid content of FPGA memory blocks with an asymptotically constant time synchronous clear ability, that can be useful for (re)initialization to one default value. A particular application can be for high-speed real-time LZ77 lossless compression algorithms, where a dictionary has to be (re)initialized before each run of the implemented compression algorithm. The method is based on two most widely used techniques for clearing the memory content: a linear passage of the memory and clearing each cell by writing a default value and creating a register field providing an (in)valid bit for each memory cell. Our solution combines these two techniques together with the use of FPGA distributed memory blocks implemented in LUTs (Look-Up Tables) to overcome negative features of each previous method without losing the most of positive features. Our solution provides a balance between the two previous techniques and exceeds them in speed, resources utilization and latency of (re)initialization.

Název v anglickém jazyce

A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time

Popis výsledku anglicky

This paper describes analysis and implementation of a new method for maintaining valid content of FPGA memory blocks with an asymptotically constant time synchronous clear ability, that can be useful for (re)initialization to one default value. A particular application can be for high-speed real-time LZ77 lossless compression algorithms, where a dictionary has to be (re)initialized before each run of the implemented compression algorithm. The method is based on two most widely used techniques for clearing the memory content: a linear passage of the memory and clearing each cell by writing a default value and creating a register field providing an (in)valid bit for each memory cell. Our solution combines these two techniques together with the use of FPGA distributed memory blocks implemented in LUTs (Look-Up Tables) to overcome negative features of each previous method without losing the most of positive features. Our solution provides a balance between the two previous techniques and exceeds them in speed, resources utilization and latency of (re)initialization.

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

—

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

ReConFig’16

ISBN

978-1-5090-3707-0

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

—

Název nakladatele

IEEE

Místo vydání

Piscataway

Místo konání akce

Cancún

Datum konání akce

30. 11. 2016

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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